Every line of the in this Question deserves a whole book dedicated to answer.You can try to find such books. You can get to it through you everyday experience, if you do your work very well.However, this is one well-known universal Answer to this:Peter Norvig, Teach Yourself Programming...

Java

C++

VHDL

Frequency Divider with VHDL

20 Aug 2012 by Carlos A. Ramos

This brief article describes a frequency divider with VHDL along with the process of calculating the scaling factor.

vhdl code for linear feedback shiftregister

11 Jan 2011 by Manfred Rudolf Bihy

Hi Helina,find the VHDL code for LFSRs there: http://sciencezero.4hv.org/science/lfsr.htm[^], the site also has the codes for MMX, ARM, C++ and BASIC.VHDL code for a LFSRsignal lfsr : std_logic_vector(14 downto 0);lfsr

VHDL

Hardware–Software Codesign of Automatic Speech Recognition System for Embedded Real-Time Applications

22 Jul 2011 by OriginalGriff

We do not do your homework: it is set for a reason. It is there so that you think about what you have been told, and try to understand it. It is also there so that your tutor can identify areas where you are weak, and focus more attention on remedial action.We are more than willing to help...

Windows

embedded

VHDL

How do i generate a clock signal to push the data inside the ram memory and read it out again usind an addressable pointer

9 Feb 2016 by Dave Kreskowiak

You're probably not going to get an answer to this question here.VHDL questions questions here are very rare and answers are even rarer.You'd be much better served by finding a forum dedicated to VHDL and hardware design.

VHDL

I need help with a verilog/vhdl code to drive sevomotor using fpga.

15 Feb 2016 by OriginalGriff

As Richard says, we're not here to do your work for you.And as it happens we have very few FPGA developers here - you might be better looking at a more "focussed" website that routinely deals with them. We are primarily software, so try Verilog or Altera themselves and see where they can...

VHDL

VHDL interleaver creation 4x4 matrix

7 May 2021 by Richard MacCutchan

If you are a beginner then maybe this will help: VHDL Tutorial - Introduction to VHDL for beginners[^].

VHDL

how we can give the input for correlation based rectangular encoder

11 Jan 2011 by Espen Harlinn

Try this link:Scholarly articles for correlation based rectangular encoder[^]It's a starting point - your question is far to general in nature. If you would show us your code, we might just understand what you're having problems with. I assume that you have put some effort into dealing...

VHDL

vhdl for rectangular encoding

11 Jan 2011 by Richard MacCutchan

You already have a suggestion here. Please do not repost the same question.

VHDL

vhdl for rectangular encoding

11 Jan 2011 by Sandeep Mewara

It does not work like this here.Here is what is expected by enquirers:1. TRY first what you want to do!2. Formulate what was done by you that looks like an issue/not working. Try them and tell if you face issues.Members will be more than happy to help like this.

VHDL

how to covert the image into 0's and 1's

12 Jan 2011 by Richard MacCutchan

I think you should spend some time reading here[^], rather than asking such vague questions.

VHDL

about software development

18 Apr 2011 by thakural

how to generate or develop a software in any language?how do one develop a platform independent software?coding is the one that is been performed on theparticular format but how to compile or combine that code in order to make a complete platfor independent software?please give a liitle...

Java

C++

VHDL

BCH encoder VHDL code wanted

15 Oct 2011 by busybee77

hello everyone!! i was trying to make a BCH encoder in VHDL with three components PISO, LFSR and SIPO.but everytime i get a lots of errors in making LFSR. can anyone help me a good and easy to understand vhdl code BCH lFSR encoder?PISO- parallel to serial shift registerLFSR - linear...

VHDL

BCH encoder VHDL code wanted

15 Oct 2011 by Mehdi Gholam

Read the following :http://home.agh.edu.pl/~jamro/bch_thesis/bch_thesis.html[^]http://comblock.com/download/com1209Asoft.pdf[^]http://gse.innalogics.com.br/publications/ICCGI2007.pdf[^]

VHDL

BCH parallel Syndrome Generator

2 Apr 2012 by busybee77

hello there!! can anyone please help me to make BCH parallel syndrome generator in VHDL. any GF will be applicable. just to understand the method.thank you.

VHDL

Digital concurrent error detection scheme

28 Jul 2012 by OriginalGriff

This is not a question.If you believe that the code is interesting, or useful, then consider posting it as an article. But be warned: Articles are moderated, and the moderation is quite strict. You can't just dump code and walk away - it takes a lot of work to get a good article together and...

Windows

embedded

VHDL

for convert binary to decimal with VHDL language i want follow this stage :

23 Dec 2012 by homa sh

for convert binary to decimal with VHDL language i want follow this stage :S1. Shift the binary number left one bit.S2. If 8 shifts have taken place, the BCD number is in the Hundreds, Tens, and Units column.S3. If the binary value in any of the BCD columns is 5 or greater,...

VHDL

AES IMPLEMENTATION USING VHDL

19 Oct 2013 by Sergey Alexandrovich Kryukov

You are posting at the wrong site. This is a totally inappropriate request, sorry.—SA

VHDL

How to verifing video camera to FPGA ?

19 Mar 2014 by Member 10681974

to implementing a real-time moving object tracking system?

VHDL

How to verifing video camera to FPGA ?

19 Mar 2014 by leon de boer

Your going to have to add a lot more detail than that if you really expect an answer.

VHDL

how to do the image compression and decompression using lzw algorithm

29 Apr 2015 by Sergey Alexandrovich Kryukov

It makes no sense at all. Both types of files are already compressed. Amazingly, GIF is compressed using the same very LZW algorithm: http://en.wikipedia.org/wiki/GIF[^].JPEG uses lossy compression algorithm, with loss of quality (which depends on parameters), so its compression factors are...

VHDL

Hello. I Need A Vhdl Source Code For Network On Chip Router

28 May 2015 by OriginalGriff

Good luck finding it!But...it doesn't quite work like that here.We do not do your work for you.If you want someone to write your code, you have to pay - I suggest you go to Freelancer.com and ask there.But be aware: you get what you pay for. Pay peanuts, get monkeys.

VHDL

Wait Statement error in VHDL

14 Jul 2015 by farhad bat

I read on bit adder in VHTL in Quartus II 9.1 from this site:http://esd.cs.ucr.edu/labs/adder/add_tst.vhd[^]first according guide I add and compile 1 bit adder,it works correctly.-- Simulation Tutorial-- 1-bit Adder-- This is just to make a reference to some common things...

VHDL

using component in process in VHDL

15 Jul 2015 by farhad bat

I write four VHDL file1) 1 bit full adder2) 8 bit full adder3) 1 bit flip flop4) accumulator1 and 2 and 3 is correct and I tested those , but I have a really big problem in accumulator!this is picture of accumulator that I want build by 1,2 and 3 :...

VHDL

which are electronic noises that effect blood pressure signal?

13 Nov 2015 by OriginalGriff

This isn't a question we can answer.It's not just that is rather vague and relies on physiological activities that most of us have no real knowledge of - it's that we have no idea how your filtering is going to work. There are so many ways to use an FPGA that the question becomes meaningless!...

VHDL

which are electronic noises that effect blood pressure signal?

14 Nov 2015 by Jochen Arndt

This is more an electronics related question. Random (gaussian) noise covers all frequencies. This can't be filtered out but reduced by hardware design (e.g. choosing low noise operational amplifiers). The harware design should be also optimised to reduce noise by interfering signals (e.g. low...

VHDL

How do i generate a clock signal to push the data inside the ram memory and read it out again usind an addressable pointer

9 Feb 2016 by ahmad alhomsi

Hallo...I have written a code using VHDL to istablish an I2C connection between two micro processors one of them as a master and the other one as a slave ...so i made a slave module as a state machine and i would like to declare a RAM memory to write in and then read out from it ...BUT the...

VHDL

How to write a clock divider program with division of non-integer 1.5 , 2.5

23 Mar 2016 by Sascha Lefèvre

There's plenty of resources for this:vhdl clock divider fraction - Google Search[^]vhdl fractional divider - Google Search[^]

VHDL

I want to simulate my VHDL code but I don't know how to write a testbench code for it. Please help! ! ! !

3 Apr 2016 by animesh2110

Hello everyone I've wriiten a VHDL code for my project. It's a clock divider code. The input clock is 12MHz and output clocks are 500KHz and 9.6KHz. I want to simulate it but I don't know how to write a testbench code. Can anyone please help me!!!Thank you.The code which I have written...

VHDL

Algorithm trax winning condition

3 May 2016 by George Jonsson

First of all, don't assume everyone knows what you are talking about. We can't see your monitor and we can't read your mind.Add an explanation of what it is you want to do and add references to inform people who is not familiar with your specific topic.You are the one who wants help, so...

TurboC++

VHDL

game

How to use float in vhdl

15 Jun 2016 by Member 12584817

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.NUMERIC_STD.ALL;use IEEE.std_logic_signed.all;-- Uncomment the following library declaration if using-- arithmetic functions with Signed or Unsigned values--use IEEE.NUMERIC_STD.ALL;-- Uncomment the following library declaration...

VHDL

How to use float in vhdl

15 Jun 2016 by Richard MacCutchan

See floating point numbers in vhdl - Google Search[^].

VHDL

Non constant real valued expression is not supported.

20 Jun 2016 by Member 12584817

VHDL

LMS (least mean square) algorithm

24 Aug 2021 by Member 12584817

We are designing LMS algorithm in vhdl. We want to know how each value of X(n) comes. We have been told that X(n) is a complex number, which is the input to equalizer which comes AFTER TRAVELLING THROUGH the CHANNEL suffering from noise, pathloss etc.So the question is , will we get the value of...

VHDL

BPSK modulation. Why these particular values are used?

28 Jun 2016 by Member 12584817

library IEEE; use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;-- Entity Declarationentity bpsk_mod isPort (clk : in std_logic; -- Processing clockvalid_in : in std_logic; -- Input valid signaldata_in : in std_logic; -- Input data...

VHDL

How do I solve this error "illegal sequential statement"

21 Jul 2016 by Issa_i

library ieee;use IEEE.std_logic_1164.all;use IEEE.STD_LOGIC_ARITH.all;use IEEE.STD_LOGIC_unsigned.all;entity COUNTER_COM is port ( START: IN STD_LOGIC; LOAD: IN STD_LOGIC_VECTOR (7 DOWNTO 0); COUNTUD: IN STD_LOGIC; COUNT1ALL: IN STD_LOGIC; INPUT: IN...

VHDL

How do I solve this error "illegal sequential statement"

21 Jul 2016 by Jochen Arndt

I don't know VHDL well but you are mixing concurrent and sequential statements. You have a sequential PROCESS block using a concurrent statement (GENERATE) inside. The error tells you that there is a statement that isn't an expected sequential one.

VHDL

How to add the fixed_pkg code into the ieee_proposed library?

1 Aug 2016 by Member 12584817

We are writing a code using vhdl. Please tell us elaborately how to add the fixed_pkg code into the ieee_proposed library.The fixed package is probably found...

VHDL

How to add delays in between states in a VHDL code..?

10 Dec 2016 by Member 12891617

I am creating a code for Traffic light control. I have developed the code as given below. I need to add a delay of 10s between the states, but I don't have any idea of doing it. I have already defined time 'T' as a standard logic vector but this cannot be used to add the timing. I am going to...

VHDL

VHDL interleaver creation 4x4 matrix

7 May 2021 by JustBeginnerVHDL

So I need some help I need to write design and testbench file for VHDL. It is interleaver for 4x4 matrix, I've got input speed 10 Mbs and clock 10 Mhz. The output is a sequence 10 Mbs with also clock speed 10 Mhz. The output of interleaver...

VHDL

VHDL interleaver help needed

6 May 2021 by OriginalGriff

Repost: Deleted. Please do not repost your question; use the Improve question widget to add information or reformat it, but posting it repeatedly just duplicates work, wastes time, and annoys people. I'll delete this one.

VHDL

VHDL interleaver creation 4x4 matrix

6 May 2021 by OriginalGriff

Quote: I am bachelor of Information technology and just practicing some VHDL which I got from friends studyng Electrical engineering as I didn't had much of VHDL programming. This was one of their assigments so I got stuck with this one. So it's...

VHDL

VHDL interleaver creation 4x4 matrix

7 May 2021 by JustBeginnerVHDL

So just to give an update I have managed to resolve this actually I have kind of forgot the matrix transpose.... :embarrassed: Here is my solution: making package using arrays as followed: package newtype is type row_1 is array(0 to 3) of...

VHDL

LMS (least mean square) algorithm

24 Aug 2021 by Vanessa Victor-Linkenhoker

Use matlab to generate X(n) and d(n) and write it to a text file that the VHDL test bench uses as input to your VHDL LMS code.

VHDL

Xilinx FPGA with AVRILOS

9 Nov 2011 by grilialex

How-To Embed Xilinx FPGA Configuration Data to AVRILOS

Servomotor Control with PWM and VHDL

20 Dec 2012 by Carlos A. Ramos

Generate a PWM signal for servomotor control with VHDL.

VHDL

How to use real/floating point numbers in vhdl

16 Jun 2016 by Richard MacCutchan

See my suggestion in your original of this question: How to use float in vhdl[^].

VHDL

RC6 cryptography: how rc6 encryption decryption can be done using FPGA?

3 Nov 2011 by rutuja.yawale

please suggest vhdl code procedure for following question:how rc6 encryption decryption can be done using FPGA SPARTEN3?

VHDL

How to write a clock divider program with division of non-integer 1.5 , 2.5

23 Mar 2016 by Dave Kreskowiak

You're not likely to get an answer to this here. VHDL questions are very seldom asked and the experience pool is very low.I suggest you find a forum dedicated to the hardware you're trying to write code for and ask there.

VHDL

about software development

18 Apr 2011 by Bharat Kumar Arya

Developing a software in any language is a huge task...and cannot be described in small article...first choose any programming language and use and IDE which will help you build the application and use tools to wrap up this into an installer...As per your requirement you want some...

Java

C++

VHDL

how to covert the image into 0's and 1's

12 Jan 2011 by helina devaraj

how to covert the image into 0's and 1's

VHDL

design accumulator in VHDL

16 Jul 2015 by farhad bat

I write accumulator in VHDL , but when I build it's wave form it is a little wrong!my code contain 4 file:1) 1 bit full adder2) 8 bit adder3) 1 bit D_FF4) accumulatorthere are codes:1) 1 bit full adderLibrary ieee;Use...

VHDL

I need help with a verilog/vhdl code to drive sevomotor using fpga.

15 Feb 2016 by animesh2110

I'm doing a project in which I'm using a potentiometer to drive servomotor using FPGA. The potentiometer's output will be fed into the atmega16 microcontroller for analog to digital conversion. After conversion the 8 bit data is wirelessly and serially transmitted through the UART of Atmega16...

VHDL

Algorithm trax winning condition

3 May 2016 by Member 12493644

I need solving algorithms TRAX game.The algorithm implement Fpga I want on board.What I have tried:i can alguethim Transform to vhdl source

TurboC++

VHDL

game

VHDL 4 bit multiplier

2 Jul 2018 by Member 13895585

design BCD multiplier whit vhdl

VHDL

how we can give the input for correlation based rectangular encoder

11 Jan 2011 by helina devaraj

how we can give the input for correlation based rectangular encoder

VHDL

vhdl code for linear feedback shiftregister

11 Jan 2011 by helina devaraj

vhdl code for linear feedback shiftregister

VHDL

Hardware–Software Codesign of Automatic Speech Recognition System for Embedded Real-Time Applications

22 Jul 2011 by mekala.v

Respected sir/madam As i am doing my project regarding speech recognition. im in need of program in VHDL,or c with regards mekala.v

Windows

embedded

VHDL

data compression in fpga using variable length coding in run length encoding and bit masking

2 Apr 2012 by Member 8758025

i am working in data compression field in fpga here i am trying to reduce the memory size by compressing the configuration information how does bitmasking workwhat is the technique behind the bitmasking

VHDL

how to covert the image into 0's and 1's

6 Jan 2013 by en.hamzeh

hi where is your image data ?1- you can convert image to binary files with C++, vb,... Of course once binary file for gray scale and others for red green blue or gamma with image Width Height Resolution or other necessary Specifications.and transfer to a memory or FPGA port.2- you must...

VHDL

change bass of voice signal with vhdl

18 May 2014 by Member 10827936

i want change bass of voice signal with VHDLthe form of input signal is: {y[n]=x[n]+ 0.8y[n-1]}in fact i want accomplishment Upper Phrase.please help me.

VHDL

OFDM transceiver system and demo on Altera DE2

3 Oct 2014 by Quang Lê

Hi everyone,Can anyone give me a project about OFDM transceiver system and demo on Altera DE2 using VHDL? please. Thanks in advance.

VHDL

how to do the image compression and decompression using lzw algorithm

29 Apr 2015 by Member 11653755

I firoj bijali. I want to know how LZW algorithm is used to compress and decompress image file(.jpg or gif). Please help me.

VHDL

How to use real/floating point numbers in vhdl

16 Jun 2016 by Member 12584817

Can anyone post a vhdl code that shows addition and multiplication of real variables/signals right from usage of libraries, to declaration of signals, to the addition and multiplication code?orCan anyone post a vhdl code that shows addition and multiplication of floating point numbers...

VHDL