Hallo...
I have written a code using VHDL to istablish an I2C connection between two micro processors one of them as a master and the other one as a slave ...
so i made a slave module as a state machine and i would like to declare a RAM memory to write in and then read out from it ...
BUT the problen is that the RAm clock signal doesn't work normally
and here is the slave module code
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use IEEE.Numeric_Std.all;
entity eI2C_Comm is
port(
--reset : in std_logic; -- System Reset
--ready : in std_logic; -- back end system ready signal
start : out std_logic; -- start of the i2c cycle
--stop : out std_logic; -- stop the i2c cycle
--data_in : in std_logic_vector(7 DOWNTO 0); -- parallel data in
--data_out : out std_logic_vector(7 DOWNTO 0); -- parallel data out
--r_w : out std_logic; -- read/write signal to the reg_map bloc
data_vld : out std_logic; -- data valid from i2c
pin_vec_L : out std_logic_vector(3 downto 0);
pin_vec_H : out std_logic_vector(3 downto 0);
scl_in : in std_logic; -- SCL clock line
scl_oe : out std_logic; -- controls scl output enable
sda_in : inout std_logic; -- i2c serial data line in
sda_oe : out std_logic;
enI2C : out std_logic
);
end entity;
architecture I2C_Comm of eI2C_Comm is
signal ireset : std_logic;
signal iready : std_logic;
signal istart : std_logic;
signal istop : std_logic;
signal idata_out : std_logic_vector(7 downto 0);
signal idata_in : std_logic_vector(7 downto 0);
signal ir_w : std_logic;
signal idata_vld : std_logic;
signal pdata_vld : std_logic;
signal cdata_vld : std_logic;
signal iscl_in : std_logic;
signal iscl_oe : std_logic;
signal isda_in : std_logic;
signal isda_oe : std_logic;
signal ibuffer_in : std_logic;
signal idatareg : std_logic_vector(7 downto 0);
signal odatareg : std_logic_vector(7 downto 0);
signal iaddreg : std_logic_vector(7 downto 0);
signal sm_state : std_logic;
constant check_add : std_logic:='0';
constant write_opp : std_logic:='1';
signal I : integer;
signal RAM_SCLK : std_logic;
signal bRAM_SCLK : std_logic;
type ram_t is array (0 to 5) of std_logic_vector(7 downto 0);
signal ram : ram_t :=("10101010","10011001","01100110","00010001","00100010","00110011");
signal RAM_we : std_logic;
signal testSig : std_logic;
begin
Slave_interface: entity work.i2c_slave port map(ireset,iready,istart,istop,idata_in,idata_out,ir_w,idata_vld,iscl_in,iscl_oe,isda_in,isda_oe);
Buffer_interface: entity work.tri_buffer port map(ibuffer_in,isda_oe,isda_in);
--RAM_interface : entity work.ram_example port map(RAM_SCLK,iaddreg,ir_w,idata_i,idata_o,pin_vec_L);
--I2Cdummy : entity work.I2C_Dummy port map(iscl_in,sda_in,orout) ;
process(istart,idata_vld)
begin
if istart = '1' then
--testSig <= not testSig;
RAM_SCLK <= '0';
sm_state <= check_add;
idata_in <= odatareg;
elsif idata_vld ='1' then
RAM_SCLK <= '0';
--testSig <= not testSig;
elsif falling_edge(idata_vld) then
--testSig <= not testSig;
RAM_SCLK <= '1';
case sm_state is
when check_add =>
if ir_w = '0' then
iaddreg <= idata_out;
--RAM_SCLK <= '1';
sm_state <= write_opp;
--RAM_SCLK <= '0';
else
iaddreg <= iaddreg +1;
--RAM_SCLK <= '1';
RAM_we <= '0';
idata_in <= odatareg;
-- RAM_SCLK <= '0';
end if;
when write_opp =>
--RAM_SCLK <= '1';
RAM_we <= '1';
idatareg <= idata_out;
iaddreg <= iaddreg +1;
--RAM_SCLK <= '0';
end case;
--testSig <= not testSig;
end if;
for count_value in 0 to 3 loop
pin_vec_L(count_value) <= iaddreg(count_value) after 5 ns;
-- pin_vec_H(count_value) <= iaddreg(count_value+4) after 5 ns;
end loop;
end process;
PROCESS(bRAM_SCLK)
BEGIN
if(rising_edge(bRAM_SCLK)) then
if(RAM_we='1') then
ram(to_integer(unsigned(iaddreg)))<= idatareg;
end if;
odatareg <= ram(to_integer(unsigned(iaddreg)));
end if;
END PROCESS;
--process(idata_valid,istop)
--begin
--if istop ='1' then
-- iPort_D1 <= '0';
--elsif (falling_edge(idata_valid)) then
-- iPort_D1 <= '1';
-- if(idata_out = data_b)then
-- iport_D1 <= '1';
--else iport_D1 <= '0';
--end if;
--end if;
--end process;
--process(pin_vec)
--begin
--variable var : std_logic_vector(0 to 3);
--var:="1111";
--process(idata_out)
-- for I in 0 to 3 loop
--if(idata_out(0)='1' and idata_out(1)='1' and idata_out(2)='1' and idata_out(3)='1') then
-- if(idata_out(I) = '1') then
-- iport_B2 <= '1';
-- end if;
--end loop;
--end process;
--process(idata_out)
--begin
--if(idata_out =$F6) then
--for count_value in 0 to 7 loop
-- if(idata_out ="11111010") then
-- iport_B2 <= '1';
--else
-- iport_B2 <= '0';
-- end if;
--end if;
-- end loop;
--end process;
--process(isda_oe)
--begin
--if (isda_oe ='1') then
-- sda_in <= '0';
--else
--sda_in <= 'Z';
--end if;
--end process;
--sda_in <= iY and sda_in;
--data_out <= idata_out;
--idata_o <= idata_out;
--InReg <= idata_out;
--idata_in <= InReg;
--idata_in <= data_in;
--idata_in <= data_in;
--InReg <= idata_out;
--data_in <= InReg;
--idata_in <= data_in;
start <= istart;
--stop <= istop;
data_vld <= idata_vld;
--r_w <= ir_w;
--cdata_vld <= pdata_vld and idata_vld;
isda_in <= sda_in;
iscl_in <= scl_in;
sda_oe <= isda_oe;
scl_oe <= iscl_oe;
-- idata_in <= idata_out;
ireset <= '0';
iready <= '1';
ibuffer_in <= '0';
enI2C <= '1';
-- pin_vec_L <= ipin_vec_L;
bRAM_SCLK <= RAM_SCLK;
pin_vec_H(0) <= testSig;
end architecture I2C_Comm;
What I have tried:
I have written a code using VHDL to istablish an I2C connection between two micro processors one of them as a master and the other one as a slave ...
so i made a slave module as a state machine and i would like to declare a RAM memory to write in and then read out from it ...
BUT the problen is that the RAm clock signal doesn't work normally
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