library ieee;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_unsigned.all;
entity COUNTER_COM is
port (
START: IN STD_LOGIC;
LOAD: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
COUNTUD: IN STD_LOGIC;
COUNT1ALL: IN STD_LOGIC;
INPUT: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
OUTPUT: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COUNTER_COM;
ARCHITECTURE COUNT OF COUNTER_COM IS
--COMPONENT bitAdder4
--port(
--X:in STD_LOGIC_VECTOR(3 downto 0);
--Y:in STD_LOGIC_VECTOR(3 downto 0);
--C0:in STD_LOGIC;
-- S:out STD_LOGIC_VECTOR(3 downto 0);
-- C4:out STD_LOGIC);
--end COMPONENT;
COMPONENT bitAdder
port (
X:in STD_LOGIC;
Y:in STD_LOGIC;
CIN:in STD_LOGIC;
S:out STD_LOGIC;
COUT:out STD_LOGIC);
END COMPONENT;
SIGNAL CI: STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL CO: STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL LOAD1: STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
SIGNAL LOAD2: STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
SIGNAL A: STD_LOGIC_VECTOR (3 DOWNTO 0) := "0001";
SIGNAL B: STD_LOGIC_VECTOR (3 DOWNTO 0) := "1111";
SIGNAL SU: STD_LOGIC_VECTOR (3 DOWNTO 0);
BEGIN
PROCESS (START,LOAD, INPUT, COUNTUD, COUNT1ALL,LOAD1, LOAD2)
BEGIN
IF (LOAD = 0) THEN
IF COUNTUD = '1' THEN
LOAD1 <= "1001";
LOAD2 <= "1001";
ELSE LOAD1 <= "0000";
LOAD2 <= "0000";
END IF;
ELSE
FOR X IN 0 TO 3 LOOP
LOAD1(X) <= LOAD(X);
LOAD2(X) <= LOAD (X+4);
END LOOP;
END IF;
IF (START= '1') THEN
IF (COUNTUD = '1') THEN
IF (LOAD1 /= "1001") THEN
G1: FOR q IN 0 TO 4 GENERATE
U1: bitAdder PORT MAP (X=> LOAD1(0), Y=>A(q),CIN => CI(q),COUT => CO(q), S => SU(q) );
--U1A: bitAdder PORT MAP (X=> LOAD1(1), Y=>A(1),CIN => CI(1),COUT => CO(1), S => SU(1) );
--U1B: bitAdder PORT MAP (X=> LOAD1(2), Y=>A(2),CIN => CI(2),COUT => CO(2), S => SU(2) );
--U1C: bitAdder PORT MAP (X=> LOAD1(3), Y=>A(3),CIN => CI(3),COUT => CO(3), S => SU(3) );
END GENERATE;
LOAD1<= SU;
ELSIF (LOAD1 = "1001") THEN
LOAD1 <= "0000";
G2: FOR q IN 0 TO 4 GENERATE
U2: bitAdder PORT MAP (X=> LOAD1(q), Y=>A(q),CIN => CI(q),COUT => CO(q), S => SU(q) );
--U2A: bitAdder PORT MAP (X=> LOAD1(1), Y=>A(1),CIN => CI(1),COUT => CO(1), S => SU(1) );
--U2B: bitAdder PORT MAP (X=> LOAD1(2), Y=>A(2),CIN => CI(2),COUT => CO(2), S => SU(2) );
--U2C: bitAdder PORT MAP (X=> LOAD1(3), Y=>A(3),CIN => CI(3),COUT => CO(3), S => SU(3) );
end generate;
LOAD2 <= SU;
END IF;
ELSE
IF (LOAD1 /= "0000") THEN
G3: FOR q IN 0 TO 4 GENERATE
U3: bitAdder PORT MAP (X=> LOAD1(q), Y=>B(q),CIN => CI(q),COUT => CO(q), S => SU(q) );
--U3A: bitAdder PORT MAP (X=> LOAD1(1), Y=>B(1),CIN => CI(1),COUT => CO(1), S => SU(1) );
--U3B: bitAdder PORT MAP (X=> LOAD1(2), Y=>B(2),CIN => CI(2),COUT => CO(2), S => SU(2) );
--U3C: bitAdder PORT MAP (X=> LOAD1(3), Y=>B(3),CIN => CI(3),COUT => CO(3), S => SU(3) );
END GENERATE;
LOAD1 <= SU;
ELSIF (LOAD1 = "0000") THEN
LOAD1 <= "1001";
G4: FOR q IN 0 TO 4 GENERATE
U4: bitAdder PORT MAP (X=> LOAD2(q), Y=>B(q),CIN => CI(q),COUT => CO(q), S => SU(q) );
--U4A: bitAdder PORT MAP (X=> LOAD2(1), Y=>B(1),CIN => CI(1),COUT => CO(1), S => SU(1) );
--U4B: bitAdder PORT MAP (X=> LOAD2(2), Y=>B(2),CIN => CI(2),COUT => CO(2), S => SU(2) );
--U4C: bitAdder PORT MAP (X=> LOAD2(3), Y=>B(3),CIN => CI(3),COUT => CO(3), S => SU(3) );
END GENERATE;
LOAD2 <= SU;
END IF;
END IF;
ELSE NULL;
END IF;
END PROCESS;
END COUNT;
What I have tried:
I am working of BCD counter and I am getting this error "COMBINATIONAL.vhdl(67): Illegal sequential statement" I tried to initialize q outside the process and also I tried not using q but it