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Questions


1
answer

LMS (least mean square) algorithm

23-Jun-16 22:53pm - updated 24-Aug-21 5:42am
3
answers

VHDL interleaver creation 4x4 matrix

6-May-21 22:08pm - updated 7-May-21 11:35am
0
answers

How to add delays in between states in a VHDL code..?

9-Dec-16 21:11pm - updated 10-Dec-16 0:49am
0
answers

How to add the fixed_pkg code into the ieee_proposed library?

1-Aug-16 22:16pm - updated 1-Aug-16 22:17pm
1
answer

How do I solve this error "illegal sequential statement"

21-Jul-16 12:16pm - updated 21-Jul-16 21:40pm
0
answers

BPSK modulation. Why these particular values are used?

28-Jun-16 2:06am
0
answers

Non constant real valued expression is not supported.

20-Jun-16 21:19pm
1
answer

How to use real/floating point numbers in vhdl

16-Jun-16 5:55am - updated 16-Jun-16 7:18am
1
answer

How to use float in vhdl

14-Jun-16 23:01pm - updated 15-Jun-16 1:03am
1
answer

Algorithm trax winning condition

3-May-16 8:07am - updated 3-May-16 13:48pm
0
answers

I want to simulate my VHDL code but I don't know how to write a testbench code for it. Please help! ! ! !

3-Apr-16 16:38pm
1
answer

I need help with a verilog/vhdl code to drive sevomotor using fpga.

15-Feb-16 3:35am - updated 15-Feb-16 4:24am
1
answer

How do i generate a clock signal to push the data inside the ram memory and read it out again usind an addressable pointer

9-Feb-16 1:09am - updated 9-Feb-16 4:10am
0
answers

design accumulator in VHDL

16-Jul-15 0:00am
0
answers

using component in process in VHDL

15-Jul-15 12:37pm - updated 15-Jul-15 12:41pm
0
answers

Wait Statement error in VHDL

14-Jul-15 8:47am
1
answer

how to do the image compression and decompression using lzw algorithm

29-Apr-15 20:31pm - updated 29-Apr-15 20:59pm
0
answers

OFDM transceiver system and demo on Altera DE2

2-Oct-14 17:13pm - updated 3-Oct-14 17:06pm
0
answers

change bass of voice signal with vhdl

18-May-14 20:34pm
1
answer

How to verifing video camera to FPGA ?

19-Mar-14 1:12am - updated 19-Mar-14 13:29pm
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