Comments by chandrAN2& (Top 22 by date)

http://www.linfo.org/root_filesystem.html

Are you saying there is no such thing as root file system?

i didn't get what you are telling

Thanks ..I have the doubt like how the root file system is created? Say root file system contain already some file ? After mounting we are using /bin/file to launch an executable right? so how this file is already stored under /bin in the disk?

Understood , thanks. If carry flag is not cleared, did ASR instruction use the carry bit vale while right shifting?

Thanks for the info, but in the above case what is the reason for the NOP in between. There is no alignment problem here, all are 4byte ARM instructions.
And Debugging related options are not enabled here. Final is the timing issues which i don't understand,you mean due to pipelining, result may not be available for the next operation?Is that what you say. For that nop is not needed, this only results in pipeline stall for few cycles or instruction scheduling should change, compiler optimization will come into picture for instrcution scheduling. But i don't exactly get the reason for the above code generation.

https://www.cs.cornell.edu/~tomf/notes/cps104/twoscomp.html .
The above link nicely explain why the 2's complement is working for negative numbers.
Thanks for your clear explanation

Thanks Dave

sorry i didn't got it. could you please comment on the example which i mentioned above?

This problem is not always happening. Once in a while(once or twice per day) only this is happening.
It it is a compiler bug, then the issue should occur always.
This only confusing me, that's why I suspect hardware malfunction may results in this kind of behaviour.

One more doubt is how we strongly believe that hardware problem is unlikely.
Why we trust the processor or related hardware 100%(interested in knowing the answer).

I have tried few links , in most of the article mainly they are talking about basics of arm programming like registers and operating modes and all those stuffs.
But not about the arm syntax like characters used in arm assembly like =, ! etc..

particularly talking about syntax and semantics..

Any link for Arm reference Manual.

Thanks for your reply. Is both code and data are position independant. I am asking this because, based on pc relative address code may be generated for position independant loading, but for data what is the case? How position independant code come into picture for data section. Because in ARM site, it is mentioned that both code and data may be position independant. Could someone clarify?

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0203g/Bcfbbdec.html

Thanks Sergey for your brief explanation.

Thanks Richard, But if the critical section is accessible in interrupt context , we can disable interrupts, But we don't need this disable interrupts option for normal critical section of code accessible by tasks right? so in this case what will be the behavior?

I am clear with critical section or interrupt latency. I want to know how multiple tasks running with same priority creates a longer critical section duration in kernel.
It means kernel is spending lot of time inside the critical section if multiple tasks running with same priority. How multiple tasks running with same priority takes more processing time?