I am trying to make a component labelling engine in verilog. Need little help.

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Verilog

Hi, I am trying to build a Component Labelling Engine using taking input images from rom_128x8 and storing labeled data in SRAM. I have three SRAM designs: 256x8,512x8,4096x8. Which one should I use to have less area? Does anyone have an idea about how the labeling algorithm works?

Any help is appreciated.

Thank you

What I have tried:

Component Labeling Engine (CLE), which can detect object segmentation from the binary image, and give the same ID number to the same object.

The input image is a 32x32 binary image. For the binary signal, 0 represents the background, and 1 represents the object for each pixel. I have to check if those pixels with value 1 are connected or not. The connected pixels represent the same object. Those pixels are given with the same label ID from the same object. The number of label ID can be any number.

The image is already stored in the 128x8 ROM.

In my design now have to use SRAM to store the image from ROM. So, which SRAM should I use, and what algorithm I can implement?