Describe graph of a a logical circuit using postfix notation

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circuit

Verilog

Python3.6

I want to describe a logical circuit in below form
NODE_(node:id):node_function
VECTOR_(vector_id):vector_name-source_node_id:distenation_node_id

here is a example for half-adder
input:

module half_adder(input a, input b, output sum, output c);

wire mid1 = a & ~b;
wire mid2 = ~a & b;

sum = mid1 | mid2;
c = a & b;

endmodule

output:

NODE_INPUT_1: input_a
NODE_INPUT_2: input_b
NODE_OUTPUT_1: output_sum
NODE_OUTPUT_2: output_c
NODE_AND_1: and
NODE_AND_2: and
NODE_AND_3: and
NODE_NOT_1: not
NODE_NOT_2: not
NODE_OR_1: or
NODE_BRANCH_a: branch_a
NODE_BRANCH_b: branch_b
VECTOR_1: wire_a - NODE_INPUT_1:NODE_BRANCH_a--------
VECTOR_2: wire_b - NODE_INPUT_2:NODE_BRANCH_b--------
VECTOR_3: branch_a_1 - NODE_BRANCH_a:NODE_NOT_1------
VECTOR_4: branch_a_2 - NODE_BRANCH_a:NODE_AND_1
VECTOR_5: branch_a_3 - NODE_BRANCH_a:NODE_AND_3
VECTOR_6: branch_b_1 - NODE_BRANCH_b:NODE_NOT_2-------
VECTOR_7: branch_b_2 - NODE_BRANCH_b:NODE_AND_2
VECTOR_8: branch_b_3 - NODE_BRANCH_b:NODE_AND_3
VECTOR_9: not_1_out - NODE_NOT_1:NODE_AND_2
VECTOR_10: not_2_out - NODE_NOT_2:NODE_AND_1
VECTOR_11: mid1 - NODE_AND_1:NODE_OR_1
VECTOR_12: mid2 - NODE_AND_2:NODE_OR_1
VECTOR_13: or_1_out - NODE_OR_1:NODE_OUTPUT_1
VECTOR_14: and_3_out - NODE_AND_3:NODE_OUTPUT_2

I described nodes and for vectors I convert each infix description to postfix
but still don't now how can describe vectors using postfix.
how ever if you don't want to read below code you can assume I have

a b ~ &
a ~ b &
mid1 mid2 |
a b &

and want to describe graph of half adder circuit (is there any algorithm like evaluate postfix using stack or something else?)

What I have tried:

from pyparsing import *
from functools import reduce
and_counter=1
or_counter=1
not_counter=1
def add_and_counter():
    global and_counter
    and_counter+=1
def add_or_counter():
    global or_counter
    or_counter+=1
def add_not_counter():
    global not_counter
    not_counter+=1
def noding_input_output(s,loc,toks):
    nodeOutput=1
    nodeInput=1
    for i in toks:
        if i[0]=="input":
            print("NODE_INPUT_"+str(nodeInput)+": input_"+str(i[1]))
            nodeInput+=1
        else:
            print("NODE_OUTPUT_"+str(nodeOutput)+": output_"+str(i[1]))
            nodeOutput+=1

def noding_booleans(s,loc,toks):
    input_or_output=toks[0][0]
    toks=toks[0][1:]
    for j in toks:
        for k in j:
            if k==and_op:
                print("NODE_AND_"+str(and_counter)+": and")
                add_and_counter()
            elif k==or_op:
                print("NODE_OR_"+str(or_counter)+": or")
                add_or_counter()
            elif k==not_op:
                print("NODE_NOT_"+str(not_counter)+": not")
                add_not_counter()
    expr=reduce(lambda x,y:x+y,toks[2])
    expr=" ".join(toks)
    vector=infix_to_postfix(expr)
    #if input_or_output==input:


def infix_to_postfix(ins):
    preced={"~":3,"&":2,"|":2,"(":1}
    def pushOperator(component):
        while stack!=[] and \
              preced[stack[-1]]>=preced[component]:
            ans.append(stack.pop())
        stack.append(component)
    ans=[]
    stack=[]
    token=ins.split()
    for component in token:
        if component=="(":
            stack.append(component)
        elif component==")":
            while stack!=[]:
                t=stack.pop()
                if t=="(":
                    break
                ans.append(t)
        elif isOperation(component):
            while stack!=[] and preced[stack[-1]]>=preced[component]:
                ans.append(stack.pop())
            stack.append(component)
            
        else:
            ans.append(component)
    
    while stack!=[]:
        t=stack.pop()
        if t=="(":
            break
        ans.append(t)
    ans=" ".join(ans)
    return ans

def isOperation(xs):
    operation=["~","&","|"]
    for op in operation:
        if xs==op:
            return True
    return False
            
identifier=Word(srange("[a-z0-9_]"))
module_ins_name=Group(identifier)
lp=Literal("(").suppress()
rp=Literal(")").suppress()
semi=Literal(";").suppress()
assignment=Literal("=").suppress()
and_op=Literal("&").suppress()
or_op=Literal("|").suppress()
not_op=Literal("~").suppress()
input=Keyword("input").suppress()
output=Keyword("output").suppress()
wire=Keyword("wire").suppress()
module=Keyword("module").suppress()
endmodule=Keyword("endmodule").suppress()
arguments=Group(lp+delimitedList(Group(2*identifier)).setParseAction(noding_input_output)+rp)
#arguments.parseString("(input i1, input i2, output out)")
input_output_instance=Group(identifier+assignment+OneOrMore(Word(srange("[a-z0-9_()&|~]")))+semi).setParseAction(noding_booleans)
wire_definition=Group(wire+delimitedList(identifier)+semi+OneOrMore(input_output_instance))|Group(wire+input_output_instance)
output_definition=OneOrMore(input_output_instance)
wire_output_definition=OneOrMore(wire_definition)+OneOrMore(output_definition)
#print(OneOrMore(wire_definition).parseString("wire mid1= a & ~b;\nwire mid2 = ~a & b;"))
#print(output_definition.parseString("sum = mid1 | mid2;\nc = a & b;"))
#print(wire_output_definition.parseString("wire mid1= a & ~b;\nwire mid2 = ~a & b;\nsum = mid1 | mid2;\nc = a & b;"))