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GeneralHow would you slice up this turkey? Pin
CodeWraith15-May-20 2:43
CodeWraith15-May-20 2:43 
GeneralRe: How would you slice up this turkey? Pin
OriginalGriff15-May-20 4:05
mveOriginalGriff15-May-20 4:05 
GeneralRe: How would you slice up this turkey? Pin
CodeWraith15-May-20 6:08
CodeWraith15-May-20 6:08 
GeneralRe: How would you slice up this turkey? Pin
lopatir15-May-20 4:15
lopatir15-May-20 4:15 
GeneralRe: How would you slice up this turkey? Pin
CodeWraith15-May-20 6:39
CodeWraith15-May-20 6:39 
GeneralRe: How would you slice up this turkey? Pin
kalberts15-May-20 5:07
kalberts15-May-20 5:07 
GeneralRe: How would you slice up this turkey? Pin
fd975015-May-20 6:25
professionalfd975015-May-20 6:25 
GeneralRe: How would you slice up this turkey? Pin
CodeWraith15-May-20 8:49
CodeWraith15-May-20 8:49 
Member 7989122 wrote:
Another factor: This CPU, does it provide any harware signal indicating whether it is fetching instructions (code), accessing data, whether the stack register is involved in the address calculation or if you are in an interrupt handler? Many CPUs do, and you might use these signals as bank selectors. The 16 bit address could effectively be extended to 18 bits: One 64Ki code space, one 64Ki data space, one 64Ki stack space, and one 64Ki interrupt space. (So it would switch the lower 32Ki as well). Where DMA fits it would depend on the how the signals are set during DMA. Each of these four spaces might be banked. (I guess that stack and DMA would have only a single bank, but if it treated as such, the banker should be able to map the DMA bank with data buffers as a data bank accessible to "ordinary" (non-DMA/interrupt) code.


Interesting. I have to think about that. The processor indeed has that sort of signals that show what kind of bus cycle it is currently executing. These are fetch, execute, interrupt and DMA. Unlike many other CPUs, it does not give up its bus for DMA. Instead, it acts as a DMA controller during DMA cycles, and does the memory addressing itself. The device that requested the DMA just has to put its byte on the bus (or read it) as soon as the CPU responds with a DMA cycle.

Interrupt cycles get a little hairier. The interrupt cycles are only used to respond to an interrupt. The interrupt routine itself is executed with regular fetch and execute cycles.

Fetch cycles themselves are unproblematic, but execute cycles are not. They can access the stack, data or even code (in branching instructions). And then there still is the matter of calling code on another page. It's like sawing off the branch on which you are sitting and usually results in a nice crash.

Maybe I can work out a hybrid of both ideas. At first glance this looks good for DMA, but adds more problems for the other bus cycles.
I have lived with several Zen masters - all of them were cats.

His last invention was an evil Lasagna. It didn't kill anyone, and it actually tasted pretty good.

GeneralRe: How would you slice up this turkey? Pin
Rick York15-May-20 6:01
mveRick York15-May-20 6:01 
GeneralRe: How would you slice up this turkey? Pin
kalberts15-May-20 8:44
kalberts15-May-20 8:44 
GeneralRe: How would you slice up this turkey? Pin
Rick York15-May-20 10:13
mveRick York15-May-20 10:13 
GeneralRe: How would you slice up this turkey? Pin
CodeWraith15-May-20 11:34
CodeWraith15-May-20 11:34 
GeneralRe: How would you slice up this turkey? Pin
Luc Pattyn15-May-20 7:34
sitebuilderLuc Pattyn15-May-20 7:34 
GeneralPomodoro Apps Pin
Brady Kelly15-May-20 1:48
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musefan15-May-20 2:43
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W Balboos, GHB15-May-20 2:46
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musefan15-May-20 2:51
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W Balboos, GHB15-May-20 2:58
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PIEBALDconsult17-May-20 6:55
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W Balboos, GHB18-May-20 0:40
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GeneralRe: Pomodoro Apps Pin
Brady Kelly23-May-20 19:36
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RickZeeland15-May-20 2:50
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Brady Kelly23-May-20 20:14
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