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GeneralRe: Windows Memory mangement Pin
ForNow6-Mar-08 6:09
ForNow6-Mar-08 6:09 
GeneralRe: Windows Memory mangement Pin
Luc Pattyn6-Mar-08 6:54
sitebuilderLuc Pattyn6-Mar-08 6:54 
GeneralRe: Windows Memory mangement Pin
ForNow6-Mar-08 13:13
ForNow6-Mar-08 13:13 
GeneralRe: Windows Memory mangement Pin
Randor 7-Mar-08 5:54
professional Randor 7-Mar-08 5:54 
GeneralRe: Windows Memory mangement Pin
Luc Pattyn7-Mar-08 6:23
sitebuilderLuc Pattyn7-Mar-08 6:23 
GeneralRe: Windows Memory mangement Pin
Mike Dimmick7-Mar-08 15:56
Mike Dimmick7-Mar-08 15:56 
GeneralRe: Windows Memory mangement Pin
ForNow8-Mar-08 14:51
ForNow8-Mar-08 14:51 
GeneralRe: Windows Memory mangement Pin
Mike Dimmick9-Mar-08 3:26
Mike Dimmick9-Mar-08 3:26 
In 32-bit protected mode the segment registers still work. The segment registers themselves are 16 bits wide and point to segment descriptors which have 32-bit base and limit fields. The base and limit fields are interpreted as virtual addresses. The segment registers are really only for aliasing and setting protection information.

Windows doesn't bother with segmented addressing, bar one case: it uses the FS segment register to point to the thread's Thread Information Block. This means code can use FS:[0] to point to the TIB throughout, without having to perform another lookup to find out where the TIB is. All the other segment registers point to segments (of the correct type) which have a base of 0 and a limit of 0xFFFFFFFF, that is, they can reference any address in the system. SS, DS, ES and GS are all set to the same value, while CS points to a different selector as selectors differentiate between code and data.

For exception handling, 32-bit Windows uses the TIB to carry a chain of exception handlers, so if you look at disassembly of a function which has an exception handler, you'll see instructions referring to FS:[0].

In 64-bit long mode (x64), AMD decided to effectively remove the legacy segment registers apart from FS and GS. (Some operating systems used GS, I think.) The legacy segment registers still have to be set to point to segment descriptors but the base and limit aren't checked. The instructions that used to manipulate some of these registers (e.g. PUSH CS) have been removed. (Currently the opcodes do nothing but are reserved for future use.) The MOV CS,rnn instructions are now the only way of loading these registers.

The processor includes MOV CRn,rr and MOV rr,CRn instructions but they can only be executed at privilege level ('ring') 0, which means in kernel mode. I'd strongly recommend not trying to change them as the OS will get very confused. There are device driver APIs documented for mapping a user-mode buffer into the system address space if necessary. If you want to share some address space between processes, use a file mapping object (CreateFileMapping).

For a reference on all this information, you can try volume 3 of the Intel Architecture Software Developer's Manuals[^]. It's hard going but this really is the master reference.


DoEvents: Generating unexpected recursion since 1991

GeneralRe: Windows Memory mangement Pin
ForNow9-Mar-08 7:50
ForNow9-Mar-08 7:50 
QuestionDevice Firmware Upgrade (DFU) Pin
Roger Stoltz4-Mar-08 22:39
Roger Stoltz4-Mar-08 22:39 
GeneralSystem Hang while using pen drive Pin
yogesh_kumar_agarwal4-Mar-08 20:18
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GeneralRe: System Hang while using pen drive Pin
M.Nouri10-Mar-08 4:13
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QuestionBuild a DLL with DDK Pin
Member 41248731-Mar-08 3:41
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GeneralRe: Build a DLL with DDK Pin
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GeneralRe: Build a DLL with DDK Pin
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GeneralRe: Build a DLL with DDK Pin
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GeneralRe: Build a DLL with DDK Pin
JudyL_MD24-Mar-08 4:05
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GeneralRe: Build a DLL with DDK Pin
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GeneralRe: Build a DLL with DDK Pin
JudyL_MD24-Mar-08 5:18
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Generalrobotics..... Pin
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