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Wordle 580 2/6*
π©π¨β¬β¬π¨
π©π©π©π©π©
A good starter word, and a much better guess!
"I have no idea what I did, but I'm taking full credit for it." - ThisOldTony
"Common sense is so rare these days, it should be classified as a super power" - Random T-shirt
AntiTwitter: @DalekDave is now a follower!
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Wordle 580 4/6*
β¬π¨β¬π©β¬
π¨π¨β¬π©β¬
π©β¬β¬π©π©
π©π©π©π©π©
Happiness will never come to those who fail to appreciate what they already have. -Anon
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Wordle 580 4/6
π¨β¬β¬β¬β¬
π©π©β¬β¬π¨
π©π©π¨π¨π¨
π©π©π©π©π©
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β¬π¨π¨β¬π¨
π¨π¨π¨π¨β¬
π©β¬π©π©π©
π©π©π©π©π©
Life should not be a journey to the grave with the intention of arriving safely in a pretty and well-preserved body, but rather to skid in broadside in a cloud of smoke, thoroughly used up, totally worn out, and loudly proclaiming βWow! What a Ride!" - Hunter S Thompson - RIP
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Wordle 580 3/6
π©π©β¬β¬π¨
π©π©π¨π¨π¨
π©π©π©π©π©
Done in 30 seconds. I stand in awe of myself!
Get me coffee and no one gets hurt!
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Wordle 580 3/6*
β¬π¨π¨π¨β¬
β¬π©π¨π¨π¨
π©π©π©π©π©
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Wordle 580 4/6
β¬π¨β¬β¬π¨
β¬π¨π¨β¬π¨
β¬π¨π©π©π©
π©π©π©π©π©
"A little time, a little trouble, your better day"
Badfinger
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David Crosby, legendary Crosby, Stills & Nash and Byrds founder, dead at 81[^] His personal life aside, he had a wonderful voice and was part of some great music.
"the debugger doesn't tell me anything because this code compiles just fine" - random QA comment
"Facebook is where you tell lies to your friends. Twitter is where you tell the truth to strangers." - chriselst
"I don't drink any more... then again, I don't drink any less." - Mike Mullikins uncle
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Great LP, great song.
"the debugger doesn't tell me anything because this code compiles just fine" - random QA comment
"Facebook is where you tell lies to your friends. Twitter is where you tell the truth to strangers." - chriselst
"I don't drink any more... then again, I don't drink any less." - Mike Mullikins uncle
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One of my all time favorite artists - a legend, gone too soon.
/ravi
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Saw him live in Austin TX, 198??
Saw him again live in Austin TX, 2012
Every bit as good live as their records.
He lived longer than most expected.
"A little time, a little trouble, your better day"
Badfinger
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turn, turn, turn ...
Crosby played rhythm and did vocals on 'Turn [^]
Β«The mind is not a vessel to be filled but a fire to be kindledΒ» Plutarch
modified 20-Jan-23 2:04am.
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A wonderful arrangement of that song, the vocals were always great.
"the debugger doesn't tell me anything because this code compiles just fine" - random QA comment
"Facebook is where you tell lies to your friends. Twitter is where you tell the truth to strangers." - chriselst
"I don't drink any more... then again, I don't drink any less." - Mike Mullikins uncle
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Cop: that's not how field sobriety tests work.
To err is human. Fortune favors the monsters.
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From what I understand there are several types of components in a processor: in some components the data is persistent in time , it survives more than one or several CPU pulses. My guess is the registers fall in this category.
Another category is the transistors, the data from the transistors is flushed when the oscillator briefly cuts the power off.
In terms of a classical 8 bit processor (the modern processors have all the bells and whistles which makes them difficult to understand) it takes one current pulse to process one line of assembly code. When the transistor web is flooded with current math takes place and the result ends up in the registers, when the next flood takes place the current flows through transistors in a pattern dictated by the next line of ASM code picking up data saved in registers in previous floods while doing so
How accurate is this? Iβm bringing a 8 bit processor into discussion not because Iβm sure how it works but because it should be simple compared to the other ones.
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I recommend reading "Code" by Charles Petzold
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I wish I could help answer, but the best I can do is verify that one CPU cycle does equate to one machine instruction / ASM mnemonic. How registers store values across cycles is beyond me, but an interesting idea to think about.
Jeremy Falcon
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Nope. With modern CPUs it's actually possible for an instruction to be "ignored" because the execution preprocessor, which runs in parallel to the actual instruction execution unit, realizes that the instruction is an effective NOP. An example of this would be PUSH AX, POP AX, which older processors would dutifully execute and newer processors would simply cut out of the execution stream. Also, the vast majority of processor instructions, even on a RISC machine, take more than one clock cycle.
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obermd wrote: Also, the vast majority of processor instructions, even on a RISC machine, take more than one clock cycle. But then again, thanks to pipelining, over time the average number of instructions executed per cycle is often close to one. Techniques such as 'hyperthreading' could even give you more than one instruction per cycle ... on the average, over time.
One consequence of all these speedup techniques, from pipelining/hyperthreading to speculative execution and extensive operand prefetching, is that the cost of an interrupt goes up and up, the more fancy the CPUs become. Some of it is (semi)hidden, e.g. when after interrupt handling you may have to redo the prefetch that was already done before the interrupt. The interrupt cost is more than the time from acknowledge of the interrupt signal to the handler return. You also have to count the total delays of the interrupted instruction stream, where several instructions might be affected.
At least early ARM processors were much closer to a 'direct' clock cycle to instruction relationship; its much more 'tidy' instruction set would allow it (and the gate count restrictions wouldn't allow all those fancy speedup techniques). This is compared to the x86 architecture and its derivatives, where you have to spend a million transistors on such functions to make the CPU fast enough.
Since the early ARMs, that architecture has been extended and extended and extended and ... Now it is so multi-extended that I feel I can only scratch the surface of the architecture. It probably, and hopefully, isn't (yet?) as messy as the X86 derivatives, but I am not one to tell. I fear the worst ...
I have a nagging feeling that if it was possible to start completely from scratch, it would be possible to build equally fast processors that didn't take a few billion transistors to realize. (Yes, I know that a fair share of those few billions go into the quite regular CPU caches - but those are part of the speedup expenses, too!) ARM was sort of 'a fresh start', but that is long ago. Multicore 64 bit ARM CPUs are quite different from those meant to replace 8051s ... I haven't had the time to look at RISC-V in detail yet; maybe that is another 'new start', not for replacing 8051, but aware of gigabyte RAM banks, 64 bit data and other modern requirement. I am crossing my fingers
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As you can probably tell, my info on this is a bit dated. Good to know though.
obermd wrote: Also, the vast majority of processor instructions, even on a RISC machine, take more than one clock cycle.
Do you mean for just one core? I was under the impression a single core still executes instructions one at a time.
Jeremy Falcon
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> even on a RISC machine take more than one clock cycle
Which means that either the data is split in two (or more) pieces and the pieces pass through ALU one at a time or if the type of operation requires the result from a pass gets placed at the ALU entry point and the data receives one more pass
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I guess that obermd is essentially referring to various effects of pipelining. Each individual instruction may spend 5-6 (or more) clock cycles total in various stages of processing: Instruction fetch, instruction decoding, operand fetch, *instruction execution*, storing results, ... The *instruction execution* (e.g. adding) is done in a single clock cycle, but that is only a part of the processing. In parallell with this instruction doing its add (say), the previous instruction is stuffing away its results, the next instruction is having operands fetched, the one two steps behind is being decoded and the one three steps behind is being fetched.
So the CPU may be doing one add (say) per cycle, and in the same cycle one of each of the other operations, on different instructions. For one given instruction, it takes a number of cycles to have all the different processing steps done, though.
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