How do I write a makefile for qt?

See more:

C++

Linux

QT

Eclipse

makefile

first time writing a make file. i either did a one line command from command line, or just let development environment automake makefile.

i am using:

Eclipse IDE for C/C++ Developers
Version: 2018-09 (4.9.0)
Build id: 20180917-1800
OS: Linux, v.5.13.0-28-generic, x86_64 / gtk 3.24.20
Java version: 11.0.13

this is what i have been able to gather off internet:

makefile:
LINK_TARGET = GUI2
_DEPS = CGUI.h
DEPS = $(patsubst %,$(IDIR)/%,$(_DEPS))
_OBJS = CGUI.o Main.o 
OBJ = $(patsubst %,$(ODIR)/%,$(_OBJ))
# include dir ../include
IDIR = /usr/include/qt4 
CC = g++
CFLAGS = -I
# object dir ../../build/obj
ODIR = ./eclipse-workspace/GUI2
# library dir ../lib
LDIR = /usr/lib/x86_64-linux-gnu
# Define options are those defined using -D parameter (gcc), 
# like -DSOME_DEFINE=1, 
# those defines can be checked in code like: #ifdef SOME_DEFINE
#DEFINES = 

all: $(OBJS)

.PHONY: clean

clean:
	-rm  -f $(ODIR)/*.o *~ core $(INCDIR)/*~ 

# $@ expands to the rule's target, LINK_TARGET
# $^ expands to the rule's dependencies, OBJS
$(LINK_TARGET) : $(OBJS)
	$(CC) -g -o $@ $^ $(CFLAGS)
 
# Here is a Pattern Rule, often used for compile-line.
# It says how to create a file with a .o suffix, given a file with a .cpp suffix.
# The rule's command uses some built-in Make Macros:
# $@ for the pattern-matched target
# $lt; for the pattern-matched dependency
%.o : %.cpp $(DEPS)
	$(CC) -g -o $@ -c $< $(CFLAGS)

# moc
moc_%.cpp: %.h
	moc $(DEFINES) $(IDIR) $< -o $@

# Dependency Rules are often used to capture header file dependencies.
Main.o : Main.h CGUI.h
CGUI.o : CGUI.h

# Alternatively to manually capturing dependencies, several automated
# dependency generators exist.  Here is one possibility (commented out)...
# %.dep : %.cpp
#        $(CC) -M $(FLAGS) $< > $@
# include $(OBJS:.o=.dep)

i have no clue what "DEFINES =" is suppose to be.
same thing happens with "DEFINES =" and "#DEFINES ="

added in a bug to code, and get same message.

make all 
make: Nothing to be done for 'all'.

14:07:11 Build Finished. 0 errors, 0 warnings. (took 554ms)

i expected "DEFINES =" or "#DEFINES =" to throw an error, but no change.
this is about the third makefile i tried. each one a little different.

What I have tried:

i have tried looking for ways to write a makefile on internet