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I have been confused about this for a long time.As i know ,the thread switch is achieved by windows because of the cpu's support,but i actually donot know the mechanish.
Hope a little help .
thank you .
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Sergey Alexandrovich Kryukov 1-Sep-15 8:49am    
Sorry, it's good to learn the mechanism, but it would mean writing a whole book for you. Do you want to know the CPU instructions or the whole mechanism? The whole mechanism is too complicated topic to be covered in a single Quick Answer or few answers.
—SA
codeprojectddx 5-Sep-15 21:05pm    
thanks for your answer.i have read the intel manual and some other books about os,and i find that every time a context switch happens,a timer is triggered,and the handler begin handling the trap,the questions is where the handler is.i cannot find it as i find int3 trap handler.
Sergey Alexandrovich Kryukov 5-Sep-15 21:12pm    
"Every time a context switch happens,a timer is triggered" is just not true. Timer interrupts are triggered in all cases, independently from your tasks, not matter if you have one task of many.
—SA
codeprojectddx 6-Sep-15 1:34am    
is the timer hardware not exist?"Timer interrupts are triggered in all cases"means that when the cpu is executing every instruction,the interrupt can happen?
Sergey Alexandrovich Kryukov 6-Sep-15 9:51am    
The timer is the programmable device. Yes, I explained it incorrectly. I mean, you can program the timer without handling the (hardware) IRQ interrupts. In nearly all OS, the interrupt is permanently used. But it does not have to use task switch...
—SA

1 solution

Please see my comment to the question.

The idea is: you can switch the task with the instructions JMP or CALL, and it can happen by hardware interrupts. The essence of things in not in the switch instruction, but in what's the interpretation of the target address of this instructions. So, context switching lies deep in the code of the CPU architecture. In protected mode, this is nothing like real-mode segment-offset address, this is a selector-offset address, and everything else depends on how the selector is set up, descriptors. On top of it, there can be pages, page faults and handling of corresponding exceptions used for implementation of virtual memory.

Also, using selectors is related to hardware protection (again, protected mode) and protection rings (https://en.wikipedia.org/wiki/Protection_ring[^]).

In principle, you can find out original Intel manual/reference on CPU architecture. But here is where you can start:
http://www.embedded.com/design/prototyping-and-development/4025054/Managing-Tasks-on-x86-Processors[^] (good overview with pictures),
https://en.wikipedia.org/wiki/Task_state_segment[^],
https://en.wikipedia.org/wiki/Context_switch[^],
http://wiki.osdev.org/Context_Switching[^],
http://wiki.osdev.org/Interrupt_Descriptor_Table[^],
http://wiki.osdev.org/Descriptors[^],
https://www.mindshare.com/files/ebooks/x86%20Instruction%20Set%20Architecture.pdf[^].

I want to emphasize the protection rings problem, because this is practically the most important thing for your study. You cannot play with the aspects of CPU operation you are interested in if you use some conventional OS like Windows or Linux, unless you do your experiments in a kernel-mode driver, which would be utterly impractical.

Instead, you would need to install DOS (as I did when I learned this stuff), or even Windows 95/98 on top of DOS (which lacks hardware protection), or you need some other "toy OS" for your experiments. With real-mode OS, like DOS, you would need first to learn how to enter protection mode and return to real mode. As a variant of such solution, you can work on a virtual machine.

—SA
 
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